Current software automatic test generation tools use software algorithms to compute test vectors. This class of test generation tools does not guarantee 100% coverage of possible faults in an electrical circuit. Software test generation tools do not use hardware emulation methods to generate test vectors. Software algorithms for test vector generation and fault simulation are inherently sequential and require considerable effort to do operations in parallel. There is a need for an automatic test generation tool that provides 100% coverage of possible faults in an electrical circuit.
Hardware accelerators for fault simulation use internal hardware gate representations to speed up logic computations. This approach is fast but relies on brute force alone. Hardware accelerators do not use a fault specific approach for testing faults. Present hardware fault simulation tools take a great deal of time to test every fault on a gate design. Emulation-based tools for prototyping and system level testing use re-programmable circuits and devices to represent a design and offers a scheme for system level testing, by emulating the design into the actual board or system wherein the design is to be used. This approach does not address the problem of 100% coverage of faults or does not generate test vectors for later use in an actual tester for testing at time of manufacture and does not perform any fault simulation. Emulation tools are used today to test prototypes. Emulation allows an IC designer to build a programmable representation of a circuit and check logic functionality. There are no applications using emulation or programmable logic methods to simulate faults nor automatic test generation. There is no close relationship in the prior art between test generation tools and fault simulation tools.
No patents have been found that directly claim the current invention. Three related patents are:
U.S. Pat. No. 3,492,572--Programmable Electronic Circuit Testing Apparatus Having Plural Multi-Function Test Condition Generating Circuits. PA1 U.S. Pat. No. 5,058,112--Programmable Fault Insertion Circuit. PA1 U.S. Pat. No. 5,257,268--Cost Function Directed Search Method for Generating Tests for Sequential Logic Circuits.
For the foregoing reasons, there is a need for a high performance automatic test generation and fault simulation device for electronic circuits.